Memory cell with non-destructive one-time programming

ABSTRACT

A one-time programmable memory cell and the programming thereof including a programming transistor which is disposed in series with a polycrystalline silicon programming resistor forming the memory element. The programming is non-destructive with respect to the polycrystalline silicon resistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of one-time programmingmemory cells (OTP) and more specifically to the forming of a one-timeprogramming memory in an integrated circuit.

2. Discussion of the Related Art

Conventionally, integrated circuit one-time programming memories are ofEPROM type and thus require specific programming circuits which are notcompatible with standard technologies of manufacturing of the MOStransistors used in integrated circuits. There also are one-timeprogramming memories formed by EEPROMs and non-erasable flash memories.

Another category of one-time programming memories is formed of fuse oranti-fuse memories. Such memories include memories formed of apolysilicon bar or track which is submitted to a very high current tophysically deteriorate the polysilicon and open the circuit. Suchone-time programming memory cells require very high currents (on theorder of one hundred milliamperes). This considerably limits their use.Further, the programming performed on a fuse-type cell is opticallyvisible, which is detrimental to the security of a binary code embeddedin an integrated circuit and masked in a one-time programming memory.

A similar disadvantage exists with memories of EPROM or EEPROM type,that is, a detection of the state of the storage cells is possible bymeans of an electronic scanning microscope which can detect thedifference of accumulated charges in the floating gate transistors ofsuch memories.

The present invention aims at providing a novel one-time programmingmemory structure which overcomes the disadvantages of known structures.

The present invention more specifically aims at providing the forming ofan integrated circuit memory cell which requires no additionalmanufacturing step with respect to the steps implemented to manufactureMOS transistors in conventional technologies.

The present invention also aims at improving the security of an embeddedcode by means of a one-time programming memory cell.

The present invention also aims at providing a low-cost memory cell.

The present invention also aims at providing a one-time programmingmemory cell.

SUMMARY OF THE INVENTION

To achieve these and other objects, the present invention provides aone-time programming memory cell, comprising a transistor in series witha polysilicon resistor forming the storage element, the programmingbeing controlled by forcing the flowing of a current in the polysiliconresistor which is greater than the current for which the value of thisresistance is maximum, the programming being non-destructive for thepolysilicon resistor.

According to an embodiment of the present invention, an unprogrammedstate is, by programming, modified by decreasing in an irreversible andstable manner in the read operating current range of the cell, the valueof the programming polysilicon resistor.

According to an embodiment of the present invention, a resistive readelement is connected in parallel with said transistor.

According to an embodiment of the present invention, a resistive readelement is connected in series with said transistor.

According to an embodiment of the present invention, said transistor isused in switched mode for the programming and as a controllable resistorfor the reading.

According to an embodiment of the present invention, a terminal ofapplication of a positive voltage selectable between a read voltage andat least one programming voltage is provided.

The present invention also provides a one-time memory comprising:

a plurality of memory cells, each comprising a first transistor inseries with a resistor in polysilicon, constituting the storage element,the programming being non destructive for the polysilicon resistor; and

at least one read differential amplifier, a first input of which isconnected between at least one of the cells and a second transistor, anda second input of which receives a reference potential intermediatebetween the programmed and non-programmed states of the cells.

According to an embodiment of the present invention, the referencepotential is taken at the intermediate point of a resistive dividingbridge.

According to an embodiment of the present invention, each cell presentsa non programmed state which is, by programming, modified by decreasing,in an irreversible and stable way, in the range of the read operatingcurrents of the cell, the value of its polysilicon resistor.

According to an embodiment of the present invention, programming a cellis controlled by imposing the circulation of a current in itspolysilicon resistor that is higher than the current for which the valueof this resistor presents a maximum.

According to an embodiment of the present invention, a read resistiveelement is connected in parallel with the second transistor.

According to an embodiment of the present invention, said resistiveelement can be short-circuited by said second transistor during aprogramming of the memory cells.

According to an embodiment of the present invention, a plurality of readamplifiers receives different reference voltages and is connected bytheir first input to a plurality of cells, so as to constitute amultilevel memory differentiated by the value of the polysiliconresistors.

The present invention also provides a one-time programmable memorycomprising:

a network of memory cells, each comprising a first transistor in serieswith a polysilicon resistor constituting the storage element, theprogramming being non destructive for the polysilicon resistor; and

at least one read differential amplifier, said first transistors of thecell being interconnected in a first direction of the network to thejunction points of series connection of one resistive element and onesecond transistor between a read supply voltage terminal and the firstinput of the read amplifier, the gates of the first transistors beinginterconnected in the second direction to outputs of a row decoder.

According to an embodiment of the present invention, a second input ofthe differential amplifier receives an intermediate reference potentialwith respect to the programmed and non-programmed states of the cells.

According to an embodiment of the present invention, the referencepotential is taken at an intermediate point of a resistive dividingbridge.

According to an embodiment of the present invention, said first input ofthe amplifier is connected, via a programming selection switch, to aterminal of application of a programming voltage.

According to an embodiment of the present invention, said resistiveelements are formed of depleted transistors.

According to an embodiment of the present invention, said read voltageterminal can be switched for disconnecting, during programming, thecorresponding extremities of the interconnections in the firstdirection.

The invention also provides a method for programming the memory cellcomprising temporarily imposing, in the polysilicon resistor, theflowing of a current greater than a current for which the value of thisresistance exhibits a maximum.

According to an embodiment of the present invention, the methodcomprises the following steps:

increasing step by step the current in the polysilicon resistor; and

measuring, after each application of a greater current, the value ofthis resistor in its functional read environment.

According to an embodiment of the present invention, a predeterminedtable of correspondence between the programming current and the desiredfinal resistance to apply to the polysilicon resistor the adaptedprogramming current.

According to an embodiment of the present invention, the methodcomprising:

in a first step, using said table of correspondence to program theresistor in a value close to the desired final resistance; and

in a second step, increasing step by step the current through thepolysilicon resistor until the desired final resistance is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing objects, features and advantages of the present invention,will be discussed in detail in the following non-limiting description ofspecific embodiments in connection with the accompanying drawings, inwhich:

FIG. 1 shows a first embodiment of a one-time programming memory cellaccording to the present invention;

FIG. 2 shows a second embodiment of a one-time programming memory cellaccording to the present invention;

FIG. 3 illustrates in a partial perspective view an embodiment of apolysilicon resistor forming the storage element of a cell according tothe present invention;

FIG. 4 illustrates, in a curve network, the programming of a memory cellaccording to the present invention;

FIG. 5 shows a first embodiment of a multiple-cell memory according tothe present invention; and

FIG. 6 shows a second embodiment of a memory according to the presentinvention.

The same elements have been designated with the same references in thedifferent drawings. For clarity, only those elements that are necessaryto the understanding of the present invention have been shown in thedrawings and will be described hereafter. In particular, the circuitsexploiting the binary codes by means of the cells according to thepresent invention have not been described in detail. The presentinvention can be implemented whatever the use made of the stored code.

FIG. 1 shows a first embodiment of a one-time programming memory cellaccording to the present invention.

According to the present invention, memory cell 1 comprises, in serieswith a first terminal 2 of application of a positive supply voltage anda second terminal 3 of application of a more negative or referencesupply voltage V⁻ (generally, the ground), a programmable resistor Rpcharacteristic of the present invention, and a programming switch (here,an N-channel MOS transistor MN). Resistor Rp forms the storage elementof cell 1. The state stored in the cell is read from junction point 4 ofresistor Rp with transistor MN. The reading of the stored level isperformed as will be seen hereafter in relation with FIG. 5, bycomparison with a reference level.

DETAILED DESCRIPTION

A feature of the present invention is that resistor Rp forming thestorage element is a polysilicon resistor having a value programmable byirreversible decrease in its value, as will be discussed hereafter inrelation with FIGS. 3 and 4.

According to this embodiment, to enable reading of the state stored incell 1, a resistor Rb (shown in dotted lines in FIG. 1) is provided,which, when transistor MN is off, forms with resistor Rp avoltage-dividing bridge. Resistor Rb has been shown in dotted lines toillustrate its optionality. Indeed, it may be formed by transistor MNthen biased in a linear portion of its characteristic and not insaturation.

Transistor MN, when on, short-circuits (at least functionally) fixedresistor Rb and is used to program resistor Rp by imposing the flowingof a current therethrough. The programming current of resistor Rp isgreater than the current for which this resistance exhibits a maximumvalue. This feature of the present invention will better appear from thedescription which will be made hereafter in relation with FIGS. 3 and 4.For the moment, it should only be noted that if resistor Rp is submittedto a current greater than the current for which its value is maximum, anirreversible decrease in the value of its resistance occurs whenreturning to currents included within the nominal operating range. Thenominal range of the operating currents of a polysilicon resistor usedaccording to the present invention is smaller than some hundredmicroamperes and, most often, smaller than some ten microamperes. Theamplitude of the programming currents is on the order of onemilliampere.

The programming of a cell such as illustrated in FIG. 1 is made possibleby providing selection of the positive supply voltage applied toterminal 2 between a read voltage Vr (adapted to generating a current onthe order of one microampere) and a programming voltage Vp (adapted togenerating a current on the order of one milliampere). The selection isperformed by means of a switch K controlled by a control circuit 4(CTRL) further providing the control signal adapted to transistor MN.

FIG. 2 shows a second embodiment of a memory cell 1′ according to thepresent invention. This cell differs from the cell of FIG. 1 in that theprogramming transistor used is a P-channel MOS transistor MP. TheP-channel MOS transistor is connected between terminal 2 and read point4. Programming resistor Rp is connected between point 4 and terminal 3of application of the reference voltage. In FIG. 2, switch K and controlcircuit 4, although still present, have not been shown. Resistor Rb indotted lines has been symbolized in parallel on transistor MP.

The operation of a cell 1′ such as shown in FIG. 2 is similar to that ofcell 1 of FIG. 1. The latter however forms a preferred embodiment due tothe smaller bulk of the N-channel MOS transistor with respect to theP-channel MOS transistor.

FIG. 3 shows an embodiment of a polysilicon resistor forming a storageelement Rp of a cell characteristic of the present invention.

Such a resistor (designated as 31 in FIG. 3) is formed of a polysilicontrack (also called a bar) obtained by etching of a layer deposited on aninsulating substrate 32. Substrate 32 is indifferently directly formedof the integrated circuit substrate or is formed of an insulating layerforming an insulating substrate or the like for resistor 31. Resistor 31is connected, by its two ends, to conductive tracks (for example, metaltracks) 33 and 34 intended to connect the resistive bar to the otherintegrated circuit elements. The simplified representation of FIG. 3makes no reference to the different insulating and conductive layersgenerally forming the integrated circuit. To simplify, only resistivebar 31 laid on insulating substrate 32 and in contact, by the ends ofits upper surface, with the two metal tracks 33 and 34, has been shown.In practice, the connections of resistive element 31 to the otherintegrated circuit components are obtained by wider polysilicon tracksstarting from the ends of bar 31, in the alignment thereof. In otherwords, resistive element 31 is generally formed by making a section of apolysilicon track narrower than the rest of the track.

Resistance R of element 31 is given by the following formula:R=ρ(L/s),

where ρ designates the resistivity of the material (polysilicon,possibly doped) forming the track in which element 31 is etched, where Ldesignates the length of element 31, and where s designates its section,that is, its width 1 by its thickness e. Resistivity ρ of element 31depends, among others, on the possible doping of the polysilicon formingit.

Most often, upon forming of an integrated circuit, the resistors areprovided by referring to a notion of so-called square resistance R_(□).This square resistance defines as being the resistivity of the materialdivided by the thickness with which it is deposited. Taking the aboverelation giving the resistance of an element 31, the resistance is thusgiven by the following relation:R=R _(□) *L/1.

Quotient L/1 corresponds to what is called the number of squares formingresistive element 31. This represents, as seen from above, the number ofsquares of given dimension depending on the technology, put side by sideto form element 31.

The value of the polysilicon resistor is thus defined, uponmanufacturing, based on the above parameters, resulting in so-callednominal resistivities and resistances. Generally, thickness e of thepolysilicon is set by other manufacturing parameters of the integratedcircuit. For example, this thickness is set by the thickness desired forthe gates of the integrated circuit MOS transistors.

A feature of the present invention is to temporarily impose, in apolysilicon resistor (Rp) of which the value is desired to beirreversibly decreased, a programming or constraint current greater thana current for which the resistor reaches a maximum value, this currentbeing beyond the normal operating current range (in read mode) of thisresistor. In other words, the resistivity of the polysilicon isdecreased in the operating current range, in a stable and irreversiblemanner, by temporarily imposing in the corresponding resistive elementthe flowing of a current beyond the operating current range.

Another feature of the present invention is that the current used todecrease the resistance is, conversely to a fusible element,non-destructive for the polysilicon element.

FIG. 4 illustrates, with a curve network giving the resistance of apolysilicon element of the type of that shown in FIG. 3 according to thecurrent flowing therethrough, an embodiment of the present invention forprogramming the memory cell resistance.

It is assumed that the polysilicon having been used to manufactureresistive element 31 (Rp) exhibits a nominal resistivity giving element31, for the given dimensions 1, L, and e, a resistance R_(nom). Thisnominal (original) value of the resistance corresponds to the valuetaken in a stable manner by resistive element 31 in the operatingcurrent range of the system, that is, generally, for currents smallerthan 100 μA.

According to the present invention, to decrease the resistance and toswitch in an irreversible and stable manner, for example, to a value R1smaller than R_(nom), a so-called constraint current (for example, I1),greater than a current Im for which the value of resistance R of element31 is maximum without for all this being infinite, is imposed acrossresistive element 31. As illustrated in FIG. 4, once current I1 has beenapplied to resistive element 31, a stable resistance of value R1 isobtained in range A1 of operating currents of the integrated circuit. Infact, curve S_(nom) of the resistance according to the current is stablefor relatively low currents (smaller than 100 μA). This curve startsincreasing for substantially higher currents on the order of a fewmilliamperes, or even more (range A2). In this current range, curveS_(nom) crosses a maximum for value Im. The resistance thenprogressively decreases. In FIG. 4, a third range A3 of currentscorresponding to the range generally used to make fuses has beenillustrated. These are currents on the order of one tenth of an amperewhere the resistance starts abruptly increasing to become infinite.Accordingly, it can be considered that the present invention usesintermediary range A2 of currents between operating range A1 anddestructive range A3, to irreversibly decrease the resistance or morespecifically the resistivity of the polysilicon element.

Indeed, once the maximum of curve S_(nom) of the resistivity accordingto the current has been passed, the value taken by the resistance in theoperating current range is smaller than value R_(nom). The new value,for example, R1, depends on the higher value of the current (here, I1)which has been applied during the irreversible current phase. It shouldindeed be noted that the irreversible decrease performed by the presentinvention occurs in a specific programming phase, outside of the normalread operating mode (range A1) of the integrated circuit, that is,outside of the normal operation of the resistor.

If necessary, once the value of the polysilicon resistor has beenlowered to a lower value (for example, R1 in FIG. 4), an irreversibledecrease in this value may further be implemented. It is enough, toachieve this, to exceed maximum current I1 of the new curve S1 of theresistance according to the current. For example, the value of thecurrent may be increased to reach a value I2. When the current is thendecreased again, a value R2 is obtained for the resistor in its normaloperating range. The value of R2 is smaller than value R1 and, ofcourse, than value R_(nom). In the application to the memory cells ofFIGS. 1 and 2, this shows the irreversible character of the implementedprogramming. An overprogramming attempt only enhances the decrease inthe resistance value with respect to its nominal value, and thus onlyconfirms the initial programming.

It can be seen that all the curves of the resistance according to thecurrent join on the decrease slope of the resistance value, after havingcrossed the maximum of the curve. Thus, for a given resistive element(ρ, L, s), currents I1, I2, etc. which must be reached, to switch to asmaller resistance value, are independent from the value of theresistance (R_(nom), R1, R2) from which the decrease is caused. In fact,the current causes an increase in the temperature of the polysiliconelement, which causes its flow.

What has been expressed hereabove as the resistance value actuallycorresponds to a decrease in the resistivity of the polysilicon formingthe resistive element. The present inventors consider that thecrystalline structure of the polysilicon is modified in a stable mannerand that, in a way, the material is reflowed, the final crystallinestructure obtained depending on the maximum current reached.

Of course, it will be ascertained not to exceed programming currentrange A2 (on the order of a few milliamperes) to avoid destroying thepolysilicon resistor. This precaution will pose no problem in practicesince the use of polysilicon to form a fuse requires much highercurrents (on the order of one tenth of an ampere) which are notavailable once the circuit has been made.

The practical forming of a polysilicon resistor according to the presentinvention does not differ from the forming of a conventional resistor.Starting from an insulating substrate, a polysilicon layer is depositedand etched according to the dimensions desired for the resistor. Sincethe deposited polysilicon thickness is generally determined by thetechnology, the two dimensions which can be adjusted are the width andthe length. Generally, an insulator is redeposited on the polysiliconbar thus obtained. In the case of an on-line interconnection, width 1will have been modified with respect to the wider access tracks to bemore strongly conductive. In the case of an access to the ends of thebar from the top as shown in FIG. 3, vias will be made in the overlyinginsulator (not shown) of the polysilicon bar to connect contact metaltracks 33 and 34.

In practice, to have the highest resistance adjustment capacity with aminimum constraint current, a minimum thickness and a minimum width willbe desired to be used for the resistive elements. In this case, onlylength L conditions the nominal value of the resistance once thepolysilicon structure has been set. The possible doping of thepolysilicon, whatever its type, does not hinder the implementation ofthe present invention. The only difference linked to the doping is thenominal resistivity before constraint and the resistivities obtained forgiven constraint currents. In other words, for an element of givendimensions, this conditions the starting point of the resistance value,and accordingly the resistance values obtained for given constraintcurrents.

To switch from the nominal value to a lower resistance or resistivityvalue, several methods may be used according to the present invention.

According to a first embodiment, the current is progressively (step bystep) increased in the resistor. After each application of a highercurrent, it is returned to the operating current range and theresistance value is measured. As long as current point Im has not beenreached, this resistance value will remain at value R_(nom). As soon ascurrent point Im has been exceeded, there is a curve change (curve S)and the measured value when back to the operating currents becomes avalue smaller than value R_(nom). If this new value is satisfactory, theprocess ends here. If not, higher currents are reapplied to exceed thenew maximum value of the current curve. In this case, it is notnecessary to start from the minimum currents again as when starting fromthe nominal resistance. Indeed, the value of the current for which theresistance will decrease again is necessarily greater than the value ofconstraint current I1 applied to pass onto the current curve. Thedetermination of the pitch to be applied is within the abilities ofthose skilled in the art and is not critical in that it essentiallyconditions the number of possible decreases. The higher the pitch, themore the jumps between values will be high.

According to a second embodiment, the different currents to be appliedto pass from the different resistance values to smaller values arepredetermined, for example, by measurements. This predetermination takesof course into account the nature of the polysilicon used as well as,preferentially, the square resistance, that is, the resistivity of thematerial and the thickness with which it is deposited. Indeed, since thecurves illustrated by FIG. 4 may also be read as the curves of thesquare resistance, the calculated values can be transposed to thedifferent resistors of an integrated circuit defined by widths and thelengths of the resistive sections. According to this second embodiment,the value of the constraint current to be applied to the resistiveelement to decrease its value in an irreversible and stable manner canthen be predetermined.

The two above embodiments may be combined. An approximate value maythus, in a first step, be selected (from a table) and the correspondingpredetermined current may be applied. Then, in a second step, theresistance value is refined by step-by-step decreases in its value.

According to the present invention, the irreversible decrease in theresistance or resistivity can be performed after manufacturing when thecircuit is in its functional environment. In other words, controlcircuit 4 and the programming transistors described in relation withFIGS. 1 and 2 can be integrated with the memory cell(s).

The curve change, that is, the decrease in the resistance value innormal operation is almost immediate as soon as the correspondingconstraint current is applied. “Almost immediate” means a duration of afew tens or even hundreds of microseconds which are sufficient to applythe corresponding constraint to the polysilicon bar and decrease thevalue of its resistance. This empirical value depends on the (physical)size of the bar. A duration of a few milliseconds may be chosen forsecurity. Further, it can be considered that, once the minimum durationhas been reached, any additional duration of application of theconstraint current does not modify, at least at the first order, theobtained resistance. Moreover, even if in a specific application, it isconsidered that the influence of the duration of application of theconstraint cannot be neglected, the two preferred embodiments(predetermining constraint values in duration and intensity, orstep-by-step progression to the desired value) are perfectly compatiblewith the taking into account of the duration of application of theconstraint.

As a specific example of embodiment, an N⁺ doped polysilicon resistorhaving a cross-section of 0.225 square micrometer (l=0.9 μm, e=0.25 μm)and a length L of 45 micrometers has been formed. With the polysiliconused and the corresponding doping, the nominal resistance wasapproximately 6300 ohms. This corresponds to a resistance per square ofapproximately 126 ohms (50 squares). By applying to this resistor acurrent greater than three milliamperes, a decrease in its value, stablefor an operation under currents reaching 500 microamperes has beencaused. With a current of 3.1 milliamperes, the resistance has beenlowered to approximately 4500 ohms. By applying to the resistor acurrent of 4 milliamperes, the resistance has been decreased down toapproximately 3000 ohms. The obtained resistances have been the same forconstraint durations ranging from 100 microseconds to more than 100seconds.

According to a particular implementation of the invention, theconstraint current is comprised between 1 and 10 mA.

Always according to a particular implementation, the dopantconcentration in the polycrystalline silicon is comprised between 1×10¹³and 1×10¹⁶ atoms/cm³.

For example, polycrystalline silicon resistors have been made with thefollowing nominal characteristics.

Polycrystalline Crystalline Crystalline Amorphous Technology 0.18 μm0.18 μm 0.35 μm Width 0.5 μm 0.5 μm 0.9 μm Length 3.4 μm 80 μm 45 μmThickness 200 nm 200 nm 250 nm Resistance/square 80 ohms/□ 100 ohms/□115 ohms/□ Global resistance 556 ohms 16.000 ohms 5.750 ohms Dopant As =6 × 10¹⁵ As = 5 × 10¹⁵   P = 1 × 10¹³ concentration As = 4 × 10¹⁵(atoms/cm³) Constraint 5.5 mA 4.8 mA 2.75 mA current for reducing by onehalf the resistor

Of course, the above examples as well as the given orders of magnitudeof currents and resistances for the different ranges concern presenttechnologies. The currents of ranges A1, A2, and A3 may be different(smaller) for more advanced technologies and may be transposed tocurrent densities. The principle of the present invention is notmodified by this. There are still three ranges and the intermediaryrange is used to force the resistivity decrease.

Programming voltage Vp may be a variable voltage according to whetherthe programming current levels are predetermined or are unknown and mustbe obtained by a step-by-step increase.

According to an alternative embodiment, the programming current forcedin resistor Rp is set by the control (gate voltage) of the correspondingprogramming transistor, voltage Vp being then fixed.

An advantage of the present invention is that a memory cell formed bymeans of a polysilicon resistor programmable by irreversible decrease inits value is compatible with conventional MOS transistor manufacturingtechnologies. In particular, no floating gate transistor is necessary,nor any tunnel structure like for the forming of an EPROM memory.

Another advantage of the present invention is that the code stored inthe storage element is not optically detectable, conversely to apolysilicon resistor which would be used as a fuse where the physicaldamage on the silicon bar makes the programming visible.

Another advantage of the present invention is that the irreversiblemodification of the value of the programmed resistor is not destructiveand thus does not risk damaging other circuit parts. This especiallyenables providing a decrease in the value of the resistance aftermanufacturing, and even during its lifetime in its application circuit.

FIG. 5 shows the electric diagram of a memory according to an embodimentof the present invention, associating several cells of the type of thatshown in FIG. 1.

According to this embodiment, n storage elements Rp1, Rp2, . . . Rpn areprovided. All the programming resistors Rpi are individually connectedby a selection transistor TS1, TS2, TSn to terminal 2 of application ofa positive voltage. Transistors TSi are, in this example, P-channel MOStransistors and individually receive a control signal selecting theconsidered memory bit. The terminals of the resistors Rpi opposite tothe respective transistors TSi are connected together to point 4connected, by a single programming transistor MN, to reference voltage2. A read resistor Rb is connected in parallel on transistor MN. Node 4is connected to one of two inputs (for example, the inverting input) ofa differential amplifier 5 forming a sense amplifier of the memory andoutputting the state of the selected cell. The other input, (forexample, non-inverting) of differential amplifier 5 is connected to thejunction point 6 of a reference resistor Rr and of a second readresistor Rb′ connected in series between two terminals 2 and 3.

Resistors Rb and Rb′ have same values. The value of resistor Rr ischosen to range between the value of the resistors programmed at state 0(respectively 1) of the memory cells and the value of the unprogrammedresistors providing a state 1 (respectively 0). Thus, since resistors Rband Rb′ have identical values, the output of differential amplifier 5 isdifferent according to whether the selected resistor Rpi has had itsvalue irreversibly decreased by programming according to the presentinvention. Initially, since resistors Rp all have a value greater thanthe value of reference resistor Rr, the initial code is, in the exampleof FIG. 5, a sequence of high states, for a non-inverting (comparator)amplifier.

An advantage of the present invention is that the individual cell iscompatible with a serialization of different cells, as illustrated inFIG. 5, or with a putting in parallel of the cells by providing oneprogramming transistor for each cell.

Another advantage of the present invention is that the number of readcycles is not limited.

Another advantage of the present invention is that it requires nospecific technology, conversely to one-time programming memorystructures of EPROM or EEPROM type.

Another advantage of the present invention is that it is not sensitiveto ultraviolet rays and thus cannot be erased by this means. Moregenerally, a memory cell programmed according to the present inventionis unerasable due to the irreversible resistance decrease performed.

According to an alternative embodiment, one or several comparators(amplifiers 5), each associated with different reference dividingbridges, may be added. A multiple-level memory is then obtained, thestored level depending on the value (for example, I1 or I2) of theprogramming current applied to the resistor Rpi of each branch. Severalprogramming voltages Vp are then provided (at least functionally, forexample, by means of resistive dividers).

Several memory cells according to the present invention may also beassociated in an array of cells to form a one-time programming memory.

FIG. 6 shows a second embodiment of a one-time programming memoryaccording to the present invention illustrating such an array network.

A network 10 of n columns and m lines of memory cells is considered.Each memory cell comprises, in series between a bit line BL1, BL2, . . .BLn and negative reference voltage V— (the ground), an N-channelprogramming transistor TP and a polysilicon programming resistor Rp. InFIG. 6, programming transistors TP and resistors Rp have been referredto with the number of the line and column to which they respectivelybelong.

Each bit line BL is connected to terminal 2 of application of a supplyvoltage Vr via an N-channel transistor Tb1, Tb2 . . . Tbn behaving asthe charge resistor Rb of the previous embodiments. In practice, theseare depleted transistors. Each bit line is connected, by its other endand via a selection transistor, respectively, Ts1, Ts2, . . . Tsn, to aninput (for example, non-inverting) of a differential sense amplifier 5,the output of which provides the state of the read cell. The other(inverting) input of amplifier 5 is connected to the midpoint of avoltage-dividing bride formed of the series association of an N-channelMOS transistor Tb′ connected to supply voltage Vr and of a resistor Rp′connected to reference voltage V−.

The respective gates of selection transistors Ts are connected toindividual outputs of a column-decoding circuit 11 (CDEC) while thegates of the programming transistors of network 10 are interconnected,for each line, to outputs of a row decoder 12 (RDEC). The decoders ofrows 12 and of columns 11 have the function, as in a conventional memorynetwork, of selecting one of the memory cells, the state of which isdesired to be read or written.

Preferably, resistor Rp′ is an also programmable polysilicon resistorand exhibits the same nominal value after manufacturing as all theresistors in the array network. Similarly, the charge resistors formedby transistors Tb and Tb′ are all identical. Upon programming of thememory cell network, reference resistor Rp′ is first programmed to avalue that may be chosen to be greater than the value of the networkresistors when they are programmed in the state different from theiroriginal state. As an alternative, resistor Rp′ is set by sizing to suchan intermediary value. However, an advantage of using a programming ofthis resistor is that this ensures, whatever the possible manufacturingdispersions, a correct parameterizing of the memory.

For the programming, the supply voltage is selected to be a programmingvoltage greater than read voltage Vr in the embodiment shown in FIG. 6.In programming, switch 13 bringing the read supply on line 2 is turnedoff and switch 14 bringing the programming voltage on line 15 ofinterconnection of selection transistors TS is turned on. The cells,resistance Rp of which is desired to be decreased, are then successivelyselected by means of the line and column decoder. The selected resistorsare applied the programming voltage via the selection transistor andprogramming transistor TP which are then in series. If desired, thenon-inverting input of amplifier 5 is associated with a protectionmeans, especially for the case where the programming voltage is greaterthan read voltage Vr. Indeed, it should be noted that the embodiment ofFIG. 6 is compatible with the use of a same voltage for the programmingand the reading. This voltage is then chosen at a sufficient level toimpose the programming. In read mode, an additional resistor linked totransistor Tb is added between the read voltage and the programmingtransistor then used as a selection transistor. Transistors Tb are thensized to introduce a series resistance much higher than that of theselection transistors, to impose a sufficient voltage drop to avoidprogramming when the supply voltage is applied on line 2 while a readingis desired to be performed.

As an alternative, programming selection transistors short-circuittransistors Tb in a programming may be provided, voltage Vp being thenapplied to terminal 2 and no longer to transistors Ts which are thenonly interconnected on the non-inverting input of amplifier 5.

The generation of programming control signals Pg of switches 13 and 14,as well as of the signals for selecting the different cells, is withinthe abilities of those skilled in the art based on the functionalindications given hereabove.

Another example of application of the present invention relates to thelocking of an integrated circuit after detection of a fraud attempt.Fraud attempt detection processes are perfectly well known. They areused to identify that an integrated circuit chip (for example, ofprepaid or not smart card type) has been attacked for, either using theprepaid units, or discovering a secret key of the chip. In such a case,the subsequent chip operation is desired to be invalidated to avoid forthe fraud to be successful. By the implementation of the presentinvention, it is possible to store a secret quantity by means of aone-time programming memory specific to the present invention. If,during the integrated circuit lifetime, a fraud attempt justifying thechip disabling is detected, the programming of one or several memorycells in an inverse state is automatically caused. By inverting even asingle bit of the secret quantity, the system will no longer be able toidentify the chip properly, which results in a full and irreversiblelocking of the chip.

To program a memory according to the present invention, several distinctphases in the product lifetime may be dissociated. For example, a firstarea (first series of resistors) programmable at the end of themanufacturing to contain a “manufacturer” code is provided. The rest ofthe memory is left available to be programmed (in one or several goes)by the user (final or not).

Of course, the present invention is likely to have various alterations,modifications, and improvement which will readily occur to those skilledin the art. In particular, the transposing of a series assembly such asillustrated in FIG. 5 to a parallel assembly is within the abilities ofthose skilled in the art based on the functional indications givenhereabove. Further, the dimensions given to the resistors forming thestorage elements and to the different current and voltage sourcesnecessary for the programming are within the abilities of those skilledin the art based on the functional indications indicated in the presentdescription. Finally, it should be noted that the present invention caneasily be transposed from one technology to another.

1. A one-time programmable memory cell, comprising a transistor inseries with a polysilicon resistor forming a storage element, whereinthe programming is controlled by forcing current to flow in thepolysilicon resistor which is greater than the current for which thevalue of the polysilicon resistor is maximum, the programming beingnon-destructive for the polysilicon resistor.
 2. The memory cell ofclaim 1, wherein an unprogrammed state is, by programming, modified bydecreasing in an irreversible and stable manner, in the read operatingcurrent range of the cell, the value of the programming polysiliconresistor.
 3. The memory cell of claim 1, wherein a resistive readelement is connected in parallel with said transistor.
 4. The memorycell of claim 1, wherein a resistive read element is connected in serieswith said transistor.
 5. The memory cell of claim 1, wherein saidtransistor is used in switched mode for programming and as acontrollable resistor for reading.
 6. The memory cell of claim 1,comprising a terminal of application of a positive voltage selectablebetween a read voltage and at least one programming voltage.
 7. A methodfor programming the memory cell of claim 1, comprising temporarilyimposing, in the polysilicon resistor, the flowing of a current greaterthan a current for which the value of a resistance exhibits a maximum.8. The method of claim 7, comprising the steps of: increasing step bystep the current in the polysilicon resistor; and measuring, after eachapplication of a greater current, the value of said polysilicon resistorin its functional read environment.
 9. The method of claim 7, comprisingusing a predetermined table of correspondence between the programmingcurrent and the desired final resistance to apply to the polysiliconresistor the adapted programming current.
 10. The method of claim 9,comprising: in a first step, using said table of correspondence toprogram the resistor in a value close to the desired final resistance;and in a second step, increasing step by step the current through thepolysilicon resistor until the desired final resistance is obtained. 11.A one-time memory, comprising: a plurality of memory cells, eachcomprising a first transistor in series with a polysilicon resistor,constituting a storage element, the programming being non destructivefor the polysilicon resistor; and at least one read differentialamplifier, a first input of which is connected between at least one ofthe cells and a second transistor, and a second input of which receivesa reference potential intermediate between the programmed and nonprogrammed states of the cells.
 12. The memory of claim 11, wherein thereference potential is taken at an intermediate point of a resistivedividing bridge.
 13. The memory of claim 11, wherein each cell presentsa non programmed state which is, by programming, modified by decreasing,in an irreversible and stable way in the range of the read operatingcurrents of the cell, the value of its polysilicon resistor.
 14. Thememory of claim 11, wherein the programming of a cell is controlled byimposing the circulation of a current in its polysilicon resistor thatis higher than the current for which the value of this resistor presentsa maximum.
 15. The memory of claim 11, wherein a read resistive elementis connected in parallel with the second transistor.
 16. The memory ofclaim 15, wherein said resistive element can be short-circuited by saidsecond transistor during a programming of the memory cells.
 17. Thememory of claim 11, wherein a plurality of read amplifiers receivesdifferent reference voltages and are connected by their first input to aplurality of cells, so as to constitute a multilevel memorydifferentiated by the value of the polysilicon resistors.
 18. A one-timeprogrammable memory, comprising: a network of memory cells, eachcomprising a first transistor in series with a polysilicon resistorconstituting the storage element, the programming being non destructivefor the polysilicon resistor; and at least one read differentialamplifier, said first transistors of the cell being interconnected in afirst direction of the network to the junction points of a seriesconnection of one resistive element and one second transistor between aread supply voltage terminal and the first input of the read amplifier,the gates of the first transistors being interconnected in the seconddirection to outputs of a row decoder.
 19. The memory of claim 18,wherein a second input of the differential amplifier receives anintermediate reference potential with respect to the programmed and nonprogrammed states of the cells.
 20. The memory of claim 19, wherein thereference potential is taken at an intermediate point of a resistivedividing bridge.
 21. The memory of claim 18, wherein said first input ofthe amplifier is connected, via a programming selection switch, to aterminal of application of a programming voltage.
 22. The memory ofclaim 18, wherein said resistive elements are formed of depletedtransistors.
 23. The memory of claim 18, wherein said read voltageterminal can be switched for disconnecting, during a programming, thecorresponding extremities of the interconnections in the firstdirection.